Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric-Reference-Cited by-同舟云学术

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Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric

Published:2023-12-18 Issue: Volume: Page:1-6
ISSN:
Container-title:2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)
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Author:

Chandan Bandi Venkata¹,Dharmender ²,Subbarao Penjerla Srinivasa¹,Nigam Kaushal Kumar³

Affiliation:

1. Institute of Science and Technology, JNTUK,School of Nano Technology,Kakinada,A.P,India

2. G.L Bajaj Institute of Technology and Management,Department of Electronics and Communication Engineering,Gr. Noida,U.P,India

3. National Institute of Technology (NIT),Department of Electronics and Telecommunication Engineering,Raipur,Chhattisgarh,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10423305/10423394/10423461.pdf?arnumber=10423461

Reference23 articles.

1. Silicon surface tunnel transistor

2. Low-subthreshold-swing tunnel transistors

3. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric

4. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

5. Tunnel field-effect transistors as energy-efficient electronic switches

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