Author:
Patil Sudarshan,Bhaaskaran V.S. Kanchana
Cited by
8 articles.
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1. Reducing Power Dissipation in Adiabatic ECRL Inverter Based on All-NMOS Transistors;2024 International Conference on Green Energy, Computing and Sustainable Technology (GECOST);2024-01-17
2. A Stacked SRAM Cell with Asymmetric Threshold Voltage for Low Leakage Power Applications;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
3. Impact of High-Performance Transistor on Performance of Static Random Access Memory for Low-Voltage Applications;Proceedings of Second International Conference on Computational Electronics for Wireless Communications;2023
4. A Review on SRAM Memory Design Using FinFET Technology;International Journal of System Dynamics Applications;2022-06-10
5. Design and Performance Analysis of SRAM Circuit Using Adiabatic Logic with FinFET;2021 International Conference on Electronics, Communications and Information Technology (ICECIT);2021-09-14