Formation and 3D Stacking Process of CMOS Chips with Backside Buried Metal Power Distribution Networks
Author:
Affiliation:
1. National Institute of Advanced Industrial Science and Technology (AIST),Tsukuba-shi,Japan
2. Graduate School of Science, Technology and Innovation, Kobe University,Kobe-shi,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195670.pdf?arnumber=10195670
Reference12 articles.
1. Development of Backside Buried Metal Layer Technology for 3D-ICs
2. Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity;zhou;IEEE Design & Test of Computers,2009
3. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
4. Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance
5. A 1/2.3inch 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM;haruta;ISSCC Dig Tech Papers,2017
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