Board-level Solder Joint Reliability of QFN Packages with Enclosure and Placement Effects in Various Form Factors-Reference-Cited by-同舟云学术

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Board-level Solder Joint Reliability of QFN Packages with Enclosure and Placement Effects in Various Form Factors

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
language:
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Author:

Lau Chun-Sean¹,Hilmi Ahmad Faridzul¹,Ye Ning²,Yang Bo²

Affiliation:

1. Western Digital Corporation,Penang,Malaysia,14100

2. Western Digital Corporation,Milpitas,CA,95035

Funder

Western Digital

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816605.pdf?arnumber=9816605

Reference5 articles.

1. Solder joint fatigue models: review and applicability to chip scale packages

2. Board-Level Reliability Performance of Enterprise and Datacenter SSD Form Factor (EDSFF)

3. Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package

4. Optimization of thermal load distribution in accelerated temperature cycling tests for solder joint lifetime qualification tests

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