Author:
Karimi F.,Meleis W.,Navabi Z.,Lombardi F.
Cited by
5 articles.
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1. A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression;2014 IEEE Computer Society Annual Symposium on VLSI;2014-07
2. Test Compression;Digital System Test and Testable Design;2010-10-15
3. Reducing test power, time and data volume in SoC testing using selective trigger scan architecture;Proceedings. 16th IEEE Symposium on Computer Arithmetic
4. ATE-amenable test data compression with no cyclic scan registers;Proceedings. 16th IEEE Symposium on Computer Arithmetic
5. A Low-Power Scan-Path Architecture;2005 IEEE International Symposium on Circuits and Systems