The Analysis of Multiwall Carbon Nanotubes as Through Silicon Via by Equivalent Circuit Model at Different Operating Temperatures in Multilayers Stacking Scheme-Reference-Cited by-同舟云学术

The Analysis of Multiwall Carbon Nanotubes as Through Silicon Via by Equivalent Circuit Model at Different Operating Temperatures in Multilayers Stacking Scheme

Published:2023-06 Issue:6 Volume:70 Page:3360-3364
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Chan Y.-C.¹^ORCID,Basu Nilabh²^ORCID,Chen T.-W.¹,Tsai Y.-T.¹,Lin H.-Y.¹,Chen S.-C.³,Lee M.-H.⁴^ORCID,Liao M.-H.⁵^ORCID

Affiliation:

1. Department of Mechanical Engineering, National Taiwan University, Taipei, Taiwan

2. Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

3. Department of Materials Engineering and Center for Plasma and Thin Film Technologies, Ming Chi University of Technology, Taipei, Taiwan

4. Graduate Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei, Taiwan

5. Department of Mechanical Engineering and the Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

Funder

Ministry of Science and Technology (MOST), Taiwan

Ministry of Education, Taiwan

PSMC

Intel

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10136238/10111068.pdf?arnumber=10111068

Reference22 articles.

1. Interlayer spacings in carbon nanotubes

2. The Demonstration of High-Quality Carbon Nanotubes as Through-Silicon Vias (TSVs) for Three-Dimensional Connection Stacking and Power-Via Technology

3. Dielectric surface roughness scattering induced crosstalk performance of coupled MCB interconnects

4. Electro-thermal transport in metallic single-wall carbon nanotubes for interconnect applications

5. Performance analysis of irradiation induced defected mixed CNT bundle based coupled VLSI interconnects

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