Abnormal Two-Stage Degradation Under Hot Carrier Injection With Lateral Double-Diffused MOS With 0.13-μm Bipolar-CMOS-DMOS Technology-Reference-Cited by-同舟云学术

Abnormal Two-Stage Degradation Under Hot Carrier Injection With Lateral Double-Diffused MOS With 0.13-μm Bipolar-CMOS-DMOS Technology

Published:2023-07 Issue:7 Volume:70 Page:3419-3423
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Hung Wei-Chun¹^ORCID,Tu Yu-Fa²^ORCID,Chang Ting-Chang³^ORCID,Tai Mao-Chou⁴^ORCID,Chen Kuan-Hsu¹,Jin Fu-Yuan¹,Yeh Chien-Hung⁴,Hung Wei-Chieh¹,Chang Chin-Han⁵,Kuo Hung-Ming¹^ORCID,Lien Chen-Hsin²

Affiliation:

1. Department of Physics, National Sun Yat-sen University, Kaohsiung City, Taiwan

2. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan

3. Department of Physics, Center of Crystal Research, College of Semiconductor and Advanced Technology Research, National Sun Yat-sen University, Kaohsiung City, Taiwan

4. Department of Photonics, National Sun Yat-sen University, Kaohsiung City, Taiwan

5. Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung City, Taiwan

Funder

National Sun Yat-sen University Joint Center for High Value Instruments;

Center for Nanoscience and Nanotechnology, National Sun Yat-sen University

National Science and Technology Council in Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10159202/10136620.pdf?arnumber=10136620

Reference27 articles.

1. Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- $\mu \text{m}$ 60-V/5-V BCD Technology

2. Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process

3. Demonstration of a HV BCD technology with LV CMOS process

4. Low on-resistance high voltage thin layer SOI LDMOS transistors with stepped field plates

5. Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor