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New Power Clamp Circuit for Concurrent ESD and Surge Protections

  • Published:2023-09 Issue:9 Volume:70 Page:4538-4546
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Yang Zhaonian1ORCID,Xu Jinghao1ORCID,Fu Dongbing2,Zhang Yan3ORCID,Zhang Yue1,Yang Yuan1ORCID,Yu Ningmei1

Affiliation:

1. Shaanxi Key Laboratory of Complex System Control and Intelligent Information Processing, Xi’an University of Technology, Xi’an, China

2. Chongqing Gigachip Technology Company Ltd., Chongqing, China

3. School of Telecommunications Engineering, Xidian University, Xi’an, China

Funder

National Natural Science Foundation of China

Shaanxi innovation capability support project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. TLP characterization for testing system level ESD performance;jahanzeb;Proc EOS/ESD Symp,2010

2. Rail Clamp with Dynamic Time-Constant Adjustment

3. Investigation of product burn-in failures due to powered NPN bipolar latching of active MOSFET rail clamps;ruth;Proc EOS/ESD Symp,2013

4. Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

5. Novel Active ESD Clamps for High-Voltage Applications

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage;IEEE Transactions on Electron Devices;2024-09
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