An Innovative Program Scheme for Reducing Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
2. NAND Design Team, SK Hynix Inc., Icheon-si, South Korea
Funder
SK Hynix Inc
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10328902/10287116.pdf?arnumber=10287116
Reference9 articles.
1. The threshold voltage variation on etch angle of channel-hole in vertical NAND flash memories;kang;Proc Int Semiconductor Dev Res Symp (ISDRS),2013
2. Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory
3. Asymmetric Interference Behavior in 3D NAND Cell and the Reverse Trend Induced by Undercut of Sacrificial Nitride Film
4. A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput;lee;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018
5. Highly-reliable cell characteristics with 128-layer single-stack 3D-NAND flash memory;park;Proc Symp VLSI Technol,2021
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