A Surface Potential Based Full-Region Current Model for Doping Segregated TFETs-Reference-Cited by-同舟云学术

A Surface Potential Based Full-Region Current Model for Doping Segregated TFETs

Published:2024-01 Issue:1 Volume:71 Page:46-53
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zhang Fangxing¹^ORCID,Li Hao¹^ORCID,Wang Kaifeng²,Dai Wu¹^ORCID,Jiao Yanxin¹^ORCID,Ding Feilong¹^ORCID,Ren Ye³,Wu Yongqin³,Bu Weihai³,Huang Qianqian²^ORCID,Zhang Lining¹^ORCID,Huang Ru²

Affiliation:

1. School of Electronic and Computer Engineering, Peking University, Shenzhen, China

2. School of Integrated Circuits, Peking University, Beijing, China

3. Semiconductor Technology Innovation Center (Beijing), Beijing, China

Funder

National Natural Science Foundation of China

Shenzhen Science and Technology Project

Higher Education Discipline Innovation Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10149050.pdf?arnumber=10149050

Reference33 articles.

1. Low-Voltage Tunnel Transistors for Beyond CMOS Logic

2. First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

3. Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

4. A novel energy-efficient salicide-enhanced tunnel device technology based on 300 mm foundry platform towards AIoT applications;Wang

5. Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications

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