Compact Modeling of Process Variations in Nanosheet Complementary FET (CFET) and Circuit Performance Predictions
Author:
Affiliation:
1. Department of Electrical Engineering, East China Normal University, Shanghai, China
2. School of Microelectronics, Fudan University, Shanghai, China
Funder
National Natural Science Foundation of China
Natural Science Foundation of Chongqing
Shanghai Science and Technology Explorer Plan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10159202/10138802.pdf?arnumber=10138802
Reference35 articles.
1. Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs
2. Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation
3. Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit
4. Statistical variability and reliability in nanoscale FinFETs
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1. Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation;2023 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia);2023-10-23
2. Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors;IEEE Open Journal of Nanotechnology;2023
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