Significant Off-State Leakage Reduction for n-FinFET by Self-Adaptive TiN Etching
Author:
Affiliation:
1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10261402/10226613.pdf?arnumber=10226613
Reference21 articles.
1. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 ?m2 SRAM cell size;natarajan;IEDM Tech Dig,2014
2. Selective epitaxial channel ground plane thin SOI CMOS devices
3. The Work Function Behavior of Aluminum-Doped Titanium Carbide Grown by Atomic Layer Deposition
4. Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond;ragnarsson;Symp VLSI Technol Dig Tech Papers,2014
5. Process technological analysis for dynamic characteristic improvement of 16-nm HKMG bulk FinFET CMOS circuits
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