Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics-Reference-Cited by-同舟云学术

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Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics

Published:2023-11 Issue:11 Volume:70 Page:5983-5990
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Deshpande Aakash Ashutosh¹^ORCID,Semwal Sandeep¹,Raskin Jean-Pierre²^ORCID,Kranti Abhinav¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Low Power Nanoelectronics Research Group, CentralWorkshop Building, Indian Institute of Technology Indore, Simrol, Indore, Madhya Pradesh, India

2. ICTEAM, Université Catholique de Louvain, Louvain-la-Neuve, Belgium

Funder

Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India

2022 ASEM DUO-Belgium/Wallonia-Brussels mobility fellowship award by Académie de Recherche et d’Enseignement Supérieur (ARES), Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10294316/10250447.pdf?arnumber=10250447

Reference36 articles.

1. Venturing Electronics into Unknown Grounds

2. Improved Mobility Extraction Methodology for Reconfigurable Transistors Considering Resistive Components and Effective Drain Bias

3. Cross-shape reconfigurable field effect transistor for flexible signal routing

4. Nanoscale FinFETs with gate-source/drain underlap;trivedi;IEEE Trans Electron Devices,2005

5. A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors

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