Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS-Reference-Cited by-同舟云学术

Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS

Published:2024-01 Issue:1 Volume:71 Page:62-69
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kar Anirban¹^ORCID,Parihar Shivendra Singh¹^ORCID,Huang Jun Z.²,Zhang Huilong²,Wang Weike²^ORCID,Imura Kimihiko²,Chauhan Yogesh Singh¹^ORCID

Affiliation:

1. Department of Electrical Engineering, IIT Kanpur, Kanpur, NanoLab, India

2. MaxLinear Inc., Carlsbad, CA, USA

Funder

Swarnajayanti Fellowship of the Department of Science and Technology (DST), Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10091880.pdf?arnumber=10091880

Reference46 articles.

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2. Sub-20 nm CMOS FinFET technologies

3. FinFET scaling to 10 nm gate length

4. A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects;Auth;IEDM Tech. Dig.,2017

5. A 7 nm FinFET technology featuring EUV patterning and dual strained high mobility channels;Xie;IEDM Tech. Dig.,2016

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs;IEEE Journal of the Electron Devices Society;2024

2. Analog/RF and Linearity Performance Assessment of a Negative Capacitance FinFET Using High Threshold Voltage Techniques;IEEE Transactions on Nanotechnology;2023