Performance Evaluation of FFT through Adaptive Hold Logic (AHL) Booth Multiplier-Reference-Cited by-同舟云学术

Performance Evaluation of FFT through Adaptive Hold Logic (AHL) Booth Multiplier

Published:2023-01-24 Issue: Volume: Page:
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Container-title:2023 International Conference for Advancement in Technology (ICONAT)
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Author:

Mahesh Banisetti Venkata¹,Srivasarao Talla¹

Affiliation:

1. Aditya Engineering College,Dept.of Electronics and Comm Engg.,Surampalem

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10079844/10079947/10080290.pdf?arnumber=10080290

Reference19 articles.

1. Design and Performance Analysis of Multipliers using Different Logic Styles

2. AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators

3. Fault Tolerant Parallel Filters Based on Error Correction Codes

4. A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT;zhang;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2016

5. A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations;li;Circuits and Systems (ISCAS) 2016 IEEE International Symposium on,2016

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