A Mismatch Error Calibration Method for 14-bit 500MS/s Time-interleaved Charge-Domain ADC
Author:
Affiliation:
1. No.58 Research Institute, China Electronic Technology Group Corporation,Wuxi,China
2. Engineering Technology Research Center of Intelligent Microsystems Anhui Province,Huangshan,China
Funder
National Science Foundation
Anhui Provincial Department of Education
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011365.pdf?arnumber=10011365
Reference14 articles.
1. A 12-bit 250-MS/s charge-domain pipelined analog-to-digital converter with feed-forward common-mode charge control
2. 4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC[J];xue;Journal of Electronics & Information Technology,2020
3. A 10-bit 250MS/s Charge-Domain Pipelined ADC with Replica Controlled PVT Insensitive BCT Circuit[J];songren;Journal of Semiconductors,2015
4. Low power time-interleaved 12bit 500MS/s charge domain ADC[J];zhenhai;Journal of Xidian University,2017
5. A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration
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