A 12-Bit 100MSps Asynchronous SAR ADC with Improved Split Capacitive DAC
Author:
Affiliation:
1. Anhui University,School of Electronics and Information Engineering,Hefei,China,230601
2. East China Research Institute of Electronic Engineering,Hefei,China,230601
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011375.pdf?arnumber=10011375
Reference10 articles.
1. A 12-bit 50-MS/s 3.3-mW SAR ADC low-frequency input (decimated by 25) with back ground digital calibration;liu;IEEE CICC Dig of Technical Papers,2010
2. Low‐power successive approximation ADC using split‐monotonic capacitive DAC
3. A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
4. A 0.9-V 12-bit 100MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS;luo;IEEE Trans Very Large Scale Integration Systems,0
5. A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching
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