Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V-Reference-Cited by-同舟云学术

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Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V

Published:2023-05-28 Issue: Volume: Page:
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Container-title:ICC 2023 - IEEE International Conference on Communications
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Author:

Chen Yulong¹,Pei YanJie²,Lu Xiang¹,Shi Mengyao¹

Affiliation:

1. Institute of Information Engineering, CAS School of Cyber Security, University of CAS,Beijing,P.R. China

2. Beijing Institute of Computer Technology and Application,Beijing,P.R. China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10278505/10278554/10279122.pdf?arnumber=10279122

Reference24 articles.

1. Design and implementation of SM3 algorithm on FPGA;ding;Microcomputer & Its Applications,2012

2. Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$

3. Hardware Design and Implementation of SM3 Hash Algorithm for Financial IC Card

4. A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over $\mathbb{F}_p$

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Custom RISC-V Based SOC Chip for Commodity Barcode Identification;IEEE Access;2024

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