Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration-Reference-Cited by-同舟云学术

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Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration

Published:2022-01-17 Issue: Volume: Page:
ISSN:
Container-title:2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
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Author:

Lee Sung-Yun¹,Kim Daeyeon¹,Min Kyungjun¹,Kang Seokhyeong¹

Affiliation:

1. Pohang University of Science and Technology,Dept. of Electrical Engineering,Pohang,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712482.pdf?arnumber=9712482

Reference33 articles.

1. Comprehensive Analysis of the Impact of Via Design on High-Speed Signal Integrity;chang;Proc IEEE Electronics Packaging Technology Conference,2007

2. Minimizing reflections and cross-talk in chip packages

3. Shielding Methodologies in the Presence of Power/Ground Noise

4. TRANSIENT ANALYSIS OF MICROSTRIP â LIKE INTERCONNECTIONS GUARDED BY GROUND TRACKS

5. Chiplet Heterogeneous Integration Technology—Status and Challenges

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