Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm-Reference-Cited by-同舟云学术

Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm

Published:2022-01-17 Issue: Volume: Page:
ISSN:
Container-title:2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
language:
Short-container-title:

Author:

Song Ling-Yen¹,Kuo Tung-Chieh¹,Wang Ming-Hung¹,Liu Chien-Nan Jimmy¹,Huang Juinn-Dar¹

Affiliation:

1. Institute of Electronics, National Yang Ming Chiao Tung University,Hsinchu City,Taiwan,R.O.C.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712559.pdf?arnumber=9712559

Reference22 articles.

1. HOLMES: Capturing the Yield Optimized Design Space Boundaries of Analog and RF Integrated Circuits;de smedt;IEEE Design Automation and Test in Europe,2003

2. Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

3. Yield-Driven Iterative Robust Circuit Optimization Algorithm;yan;IEEE Design Automation Conf,2009

4. Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

5. Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Graph Theory Based Machine Learning for Analog Circuit Design;2023 28th International Conference on Automation and Computing (ICAC);2023-08-30

2. Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing;IEEE Access;2023