A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning-Reference-Cited by-同舟云学术

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A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning

Published:2022-01-17 Issue: Volume: Page:
ISSN:
Container-title:2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
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Author:

Abouelyazid Mohamed Saleh¹,Hammouda Sherif²,Ismail Yehea³

Affiliation:

1. Siemens EDA American University in Cairo,Cairo,Egypt

2. Siemens EDA,Cairo,Egypt

3. American University in Cairo,Cairo,Egypt

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712514.pdf?arnumber=9712514

Reference15 articles.

1. A Novel Customized RC Tightened Corner Modeling Methodology Using Statistical SPICE Simulation in Advanced FinFET Technology

2. Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Testing Significance of Layout Dependent Impacts on Silicon Chips Performance;2023 3rd International Conference on Intelligent Technologies (CONIT);2023-06-23

2. Machine Learning Approaches for Electronic Design Automation in IC Design Flow;2022 Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC);2022-11-10

3. CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Interconnect Capacitance Extraction;ACM Transactions on Design Automation of Electronic Systems;2022-09-26

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