Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- $\kappa$/Metal-Gate Device Structures-Reference-Cited by-同舟云学术

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Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- $\kappa$/Metal-Gate Device Structures

Published:2007-07 Issue:7 Volume:28 Page:558-561
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Singh N.,Fang W.W.,Rustagi S.C.,Budharaju K.D.,Teo S.H.G.,Mohanraj S.,Lo G.Q.,Balasubramanian N.,Kwong D.-L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/4252183/04252220.pdf?arnumber=4252220

Cited by 37 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Novel Postgate Single Diffusion Break Integration in Gate-All-Around Nanosheet Transistors to Achieve Remarkable Channel Stress for N/P Current Matching;IEEE Transactions on Electron Devices;2022-03

3. Advancement and challenges in MOSFET scaling;Materials Science in Semiconductor Processing;2021-11

4. Investigation of Gate-Stress Engineering in Negative Capacitance FETs Using Ferroelectric Hafnium Aluminum Oxides;IEEE Transactions on Electron Devices;2019-02

5. Photo absorption enhancement in strained silicon nanowires: An atomistic study;Journal of Applied Physics;2017-07-21

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