Design of a Digital Decimation Filter with High Speed and Low Complexity-Reference-Cited by-同舟云学术

Design of a Digital Decimation Filter with High Speed and Low Complexity

Published:2021-10-29 Issue: Volume: Page:
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Container-title:2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)
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Author:

Li Xiaochen,Shang Ying,Zhao Ruilian,Jiang Beili

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9697107/9697111/09697215.pdf?arnumber=9697215

Reference20 articles.

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4. Multilevel implementation of digital decimation filter in ?-? ADC;ma;Journal of Tianjin University Natural Science and Engineering Technology,2007

5. Efficient VLSI design and implementation of decimation filter for 2nd ?-? AD converter;peng;Acta Scientiarum Naturalium Universitatis Pekinensis,2007

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