Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/1839/00050294.pdf?arnumber=50294
Cited by 29 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of Booth Multiplier based Conventional and Short Word Length FIR Filter;Mehran University Research Journal of Engineering and Technology;2018-07-01
2. Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers;2013 IEEE 43rd International Symposium on Multiple-Valued Logic;2013-05
3. Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry;IEICE Transactions on Electronics;2007-04-01
4. Nonrecoded trinary signed-digit multiplication based on digit grouping and pixel assignment;Optics Communications;2004-01
5. Evolutionary Synthesis of Arithmetic Circuit Structures;Artificial Intelligence in Logic Design;2004
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