Synchronous Mirror Delay for Multiphase Locking-Reference-Cited by-同舟云学术

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Synchronous Mirror Delay for Multiphase Locking

Published:2004-01 Issue:1 Volume:39 Page:150-156
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yoon Y.J.,Kwon H.I.,Lee J.D.,Park B.G.,Kim N.S.,Cho U.R.,Byun H.G.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/28187/01261297.pdf?arnumber=1261297

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element;Integration;2024-05

2. A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-10

3. A high-precision synchronization circuit for clock distribution;Journal of Semiconductors;2015-10

4. A delay-locked loop with digital background calibration;2009 IEEE Asian Solid-State Circuits Conference;2009-11

5. A DLL-Based Variable-Phase Clock Buffer;IEEE Transactions on Circuits and Systems II: Express Briefs;2007-12

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