A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS-Reference-Cited by-同舟云学术

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A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

Published:2004-11 Issue:11 Volume:39 Page:1862-1872
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

van de Beek R.C.H.,Vaucher C.S.,Leenaerts D.M.W.,Klumperink E.A.M.,Nauta B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/29672/01347317.pdf?arnumber=1347317

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3. A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture;IEEE Journal of Solid-State Circuits;2016-06

4. A low reference spur quadrature phase-locked loop for UWB systems;Journal of Semiconductors;2011-11

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