Design analysis and circuit enhancements for high-speed bipolar flip-flops-Reference-Cited by-同舟云学术

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Design analysis and circuit enhancements for high-speed bipolar flip-flops

Published:2005-05 Issue:5 Volume:40 Page:1166-1174
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Collins T.E.,Manan V.,Long S.I.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/30788/01425724.pdf?arnumber=1425724

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Bipolar latch with compensated keep‐alive current;The Journal of Engineering;2015-03

2. A 12.4-mW 4.5-Gb/s Receiver With Majority-Voting 1-Tap Speculative DFE in 0.13- $\mu\hbox{m}$ CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2013-12

3. A 28.5–32-GHz Fast Settling Multichannel PLL Synthesizer for 60-GHz WPAN Radio;IEEE Transactions on Microwave Theory and Techniques;2008-05

4. Static Frequency Divider with Enhanced Frequency Performance;2008 IEEE Workshop on Microelectronics and Electron Devices;2008-04

5. A 15-GHz 7-channel SiGe:C PLL for 60-GHz WPAN Application;2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium;2007-06

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