Design considerations for soft embedded programmable logic cores-Reference-Cited by-同舟云学术

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Design considerations for soft embedded programmable logic cores

Published:2005-02 Issue:2 Volume:40 Page:485-497
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wilton S.J.E.,Kafafi N.,Wu J.C.H.,Bozman K.A.,Aken'Ova V.O.,Saleh R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/30218/01388638.pdf?arnumber=1388638

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource;Cryptography;2024-04-06

2. Top-down Physical Design of Soft Embedded FPGA Fabrics;The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2021-02-17

3. A review on embedded field programmable gate array architectures and configuration tools;TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES;2020-01-27

4. Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug;ACM Transactions on Design Automation of Electronic Systems;2018-12-21

5. An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug;ACM SIGARCH Computer Architecture News;2017-01-11

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