Clock and data recovery IC for 40-Gb/s fiber-optic receiver-Reference-Cited by-同舟云学术

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Clock and data recovery IC for 40-Gb/s fiber-optic receiver

Published:2002-09 Issue:9 Volume:2 Page:1120-1125
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Georgiou G.,Baeyens Y.,Young-Kai Chen ,Gnauck A.H.,Gropper C.,Paschke P.,Pullela R.,Reinhold M.,Dorschky C.,Mattia J.-P.,von Mohrenfels T.W.,Schulien C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22087/01028089.pdf?arnumber=1028089

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Speed InP-Based Heterojunction Bipolar Transistors;Comprehensive Semiconductor Science and Technology;2011

2. Design and Implementation of Open-Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual-Mode Operation;ETRI Journal;2008-04-08

3. A 40–44 Gb/s 3$\times$ Oversampling CMOS CDR/1:16 DEMUX;IEEE Journal of Solid-State Circuits;2007-12

4. Design of high-speed clock and data recovery circuits;Analog Integrated Circuits and Signal Processing;2007-08-29

5. A 2.2 Gb/s DQPSK Baseband Receiver in 90-nm CMOS for 60 GHz Wireless Links;2007 IEEE Symposium on VLSI Circuits;2007-06

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