ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/32564/01522573.pdf?arnumber=1522573
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Fast and Accurate post-layout simulation methodology using 4nm LVS rule deck;2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS);2022-05-23
2. Robust HV Power pLDMOS Components for ESD Protection by the Drain-side Parasitic Schottky Diode and SCR Engineering;2022 International Power Electronics Conference (IPEC-Himeji 2022- ECCE Asia);2022-05-15
3. Enhance the ESD Ability of UHV 300-V Circular LDMOS Components by Embedded SCRs and the Robustness P-Body Well;IEEE Journal of the Electron Devices Society;2021
4. Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology;Solid-State Electronics;2016-10
5. Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High- $k$ /Metal Gate CMOS Process;IEEE Transactions on Electron Devices;2015-04
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