An all-digital phase-locked loop for high-speed clock generation-Reference-Cited by-同舟云学术

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An all-digital phase-locked loop for high-speed clock generation

Published:2003-02 Issue:2 Volume:38 Page:347-351
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ching-Che Chung ,Chen-Yi Lee

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/26391/01175517.pdf?arnumber=1175517

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