Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs-Reference-Cited by-同舟云学术

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Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs

Published:2020-05 Issue: Volume: Page:
ISSN:
Container-title:2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS)
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Author:

Shaikh MohammedTareeq,Soni Bhavesh,Mehta Rahul

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9118609/9120871/09121173.pdf?arnumber=9121173

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power Budget Improvement Using Floorplan Methodologies In Lower(28nm) Technology Node;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

2. Performance Enhancement of “ARP Block” using 28nm Technology node;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

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