VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors-Reference-Cited by-同舟云学术

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VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Published:2005-04 Issue:4 Volume:26 Page:258-260
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Chien-Chih Ho ,Gong-Hao Liang ,Chi-Feng Huang ,Yi-Jen Chan ,Chih-Sheng Chang ,Chih-Ping Chao

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/30534/01408035.pdf?arnumber=1408035

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-frequency noise in downscaled silicon transistors: Trends, theory and practice;Physics Reports;2022-12

2. Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2;Microelectronics Reliability;2016-05

3. Design of a CMOS multi-mode GNSS receiver VCO;Journal of Semiconductors;2012-05

4. Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus;Journal of Low Power Electronics;2011-04-01

5. A Low-Parasitic and Common-Centroid Cross-Coupled CMOS Transistor Structure for High-Frequency VCO Design;IEEE Electron Device Letters;2009-05

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