Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay-Reference-Cited by-同舟云学术

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Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Published: Issue: Volume: Page:
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Container-title:Proceedings Eighth International Symposium on High Performance Computer Architecture
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Author:

Se-Hyun Yang ,Powell M.D.,Falsafi B.,Vijaykumar T.N.

Publisher

IEEE Computer. Soc

Link

http://xplorestaging.ieee.org/ielx5/7816/21483/00995706.pdf?arnumber=995706

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Minimizing cache usage with fixed-priority and earliest deadline first scheduling;Real-Time Systems;2024-06-28

2. GA–EDA: Hybrid Design Space Exploration Engine for Multicore Architecture;Journal of Circuits, Systems and Computers;2021-02-04

3. Using Multicore Reuse Distance to Study Coherence Directories;ACM Transactions on Computer Systems;2017-10-10

4. A Review of Techniques for Optimizing Cache Energy Efficiency;VFAST Transactions on Software Engineering;2017-05-01

5. Customizable Computing;Synthesis Lectures on Computer Architecture;2015-07-06

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