An LNA with Input Power Match from 6.1 to 38.6 GHz, the Noise-Figure Minimum of 1.9 dB, and Employing Back Gate for Matching
Author:
Affiliation:
1. Electrical and Software Engineering, University of Calgary,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9862947/9862948/09863196.pdf?arnumber=9863196
Reference11 articles.
1. Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $-Match Input Network
2. Design of Low-Power Sub-2.4 dB Mean NF 5G LNAs Using Forward Body Bias in 22 nm FDSOI
3. Figures of Merit for CMOS Low-Noise Amplifiers and Estimates for Their Theoretical Limits
4. Applications of Body Biasing in Multistage CMOS Low-Noise Amplifiers
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3. A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) CMOS;2023 Sixth International Symposium on Computer, Consumer and Control (IS3C);2023-06
4. A 30–50-GHz Ultralow-Power Low-Noise Amplifier With Second-Stage Current-Reuse for Radio Astronomical Receivers in 90-nm CMOS Process;IEEE Microwave and Wireless Technology Letters;2023-05
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