High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines-Reference-Cited by-同舟云学术

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High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines

Published:2016-10 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE 5th Global Conference on Consumer Electronics
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Author:

Shih Xin-Yu,Huang Po-Chun,Chen Yu-Chun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7787085/7800304/07800526.pdf?arnumber=7800526

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hardware Architecture of Channel Encoding for 5G New Radio Physical Downlink Control Channel;ICC 2023 - IEEE International Conference on Communications;2023-05-28

2. A Modified Partially Parallel Polar Encoder Architecture;2022 6th International Conference on Electronics, Communication and Aerospace Technology;2022-12-01

3. An optimized encoding algorithm for systematic polar codes;EURASIP Journal on Wireless Communications and Networking;2019-08-01

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