Design and Implementation of a Data Stream Anonymization Core on FPGA-Reference-Cited by-同舟云学术

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Design and Implementation of a Data Stream Anonymization Core on FPGA

Published:2023-04 Issue: Volume: Page:
ISSN:
Container-title:2023 7th International Conference on Cryptography, Security and Privacy (CSP)
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Author:

Moussa Bilal¹,Chaccour Kabalan²,Mroue Mohamad³,Bouyekhf Rachid¹

Affiliation:

1. University of Technology Belfort-Montbeliard,Nanomedicine, Imagery and Therapeutics Lab.,Besançon,France

2. Antonine University,TICKET Lab.,Dept. of Computer and Communications Eng.,Hadat-Baabda,Lebanon

3. Houmal Technology Park,R&D Hardware Lab.,Multilane,Houmal,Lebanon

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10235903/10235904/10235929.pdf?arnumber=10235929

Reference15 articles.

1. (k, l)-Clustering for Transactional Data Streams Anonymization

2. A Hardware Random Number Generator, Cryptographic Hardware and Embedded Systems;tkacik;CHES,2002

3. Implementation and evaluation of an FPGA-based network data anonymizer

4. Personal data protection commission;Guide to Basic Data Anonymization Techniques,2018

5. Hardware accelerator for low-latency privacy preserving mechanism;sawada;Proceeding 4th International Conference Future Computational Technologies and Applications FUTURE COMPUTING ‘12,2012

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