FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier

Author:

Badawi Aiman,Alqarni Ali,Aljuffri Abdullah,BenSaleh Mohammed S.,Obeid Abdulfattah M.,Qasim Syed Manzoor

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. FPGA-Based 8x8 Bits Signed Multipliers Using LUTs;2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE);2023-09-24

2. RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28

3. Low Power & Area Multiplier for Deep Learning Applications;Bioscience Biotechnology Research Communications;2020-12-25

4. An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm;SN Applied Sciences;2019-10-08

5. Comparative analysis of various types of multipliers for effective low power;Microelectronic Engineering;2019-06

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