Efficient Integer DCT Architectures for HEVC-Reference-Cited by-同舟云学术

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Efficient Integer DCT Architectures for HEVC

Published:2014-01 Issue:1 Volume:24 Page:168-178
ISSN:1051-8215
Container-title:IEEE Transactions on Circuits and Systems for Video Technology
language:
Short-container-title:IEEE Trans. Circuits Syst. Video Technol.

Author:

Meher Pramod Kumar,Park Sang Yoon,Mohanty Basant Kumar,Lim Khoon Seong,Yeo Chuohao

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Media Technology

Link

http://xplorestaging.ieee.org/ielx7/76/6702488/06575105.pdf?arnumber=6575105

Cited by 131 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding;IEEE Transactions on Circuits and Systems for Video Technology;2024-07

2. Efficient 2D transform hardware architecture for the versatile video coding standard;Journal of Visual Communication and Image Representation;2024-06

3. Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding;Lecture Notes in Computer Science;2024

4. [Paper] Compressing Sign Information in DCT-based Image Coding via Deep Sign Retrieval;ITE Transactions on Media Technology and Applications;2024

5. Area and Power Efficient Transposition Buffer design for 2D-DCT Architecture in Video Applications;2023 9th International Conference on Smart Structures and Systems (ICSSS);2023-11-23

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