Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
Author:
Affiliation:
1. University of Southern California,Los Angeles,CA,USA
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10296174/10296123/10296434.pdf?arnumber=10296434
Reference46 articles.
1. HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
2. Efficient Neighbor-Sampling-based GNN Training on CPU-FPGA Heterogeneous Platform
3. A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via on-chip Dynamic Tree Management
4. HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform
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