Highly Linear Charging/Discharging of Charge Trap FET Using Regulated Single Pulse for Neural Accelerator
Author:
Affiliation:
1. Sungkyunkwan University,Department of Electrical and Computer Engineering
Funder
National Research Foundation of Korea (NRF)
IC Design Education Center(IDEC), Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10457047/10457087/10457242.pdf?arnumber=10457242
Reference9 articles.
1. Emerging Memory Technologies: Recent Trends and Prospects
2. Improved Synaptic Behavior Under Identical Pulses Using AlOx/HfO2Bilayer RRAM Array for Neuromorphic Systems
3. A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application
4. Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode
5. 20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD
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