An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery
Author:
Affiliation:
1. School of Electrical Engineering, Hanyang University,Ansan,South Korea
2. Korea Electronics Technology Institute,Convergence Signal SoC,Seongnam,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10457047/10457087/10457116.pdf?arnumber=10457116
Reference5 articles.
1. 6.1 A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology
2. A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links;Wang;ISSCC Tech. Dig.,2023
3. Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial
4. Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
5. A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference
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