Author:
Wu Chung-Bin,Wang Ching-Shun,Hsiao Yu-Kuan
Funder
Ministry of Science and Technology
Cited by
5 articles.
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1. FPGA Implementation of a Fault-Tolerant Fused and Branched CNN Accelerator With Reconfigurable Capabilities;IEEE Access;2024
2. A dynamic computational memory address architecture for systolic array CNN accelerators;2022 IEEE 24th Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys);2022-12
3. Design and Implementation of Reconfigurable Array Structure for Convolutional Neural Network Supporting Data Reuse;2022 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC);2022-11-07
4. RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks;Journal of Circuits, Systems and Computers;2022-07-07
5. AI Crowd Control Detection System Implemented on FPGA Hardware Development Platform;2022 IEEE International Conference on Consumer Electronics (ICCE);2022-01-07