Digital Image Encryption Using 256-Bit Advanced Encryption Standard Algorithm
Author:
Affiliation:
1. Delhi Technological University,Department of Electronics and Communication,New Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10141668/10141583/10141709.pdf?arnumber=10141709
Reference30 articles.
1. A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration;duran;IEEE Transactions on Circuits and Systems II Express Briefs,2022
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4. An optimized S-Box circuit architecture for low power AES design;sumio;International Workshop on Cryptographic Hardware and Embedded Systems,2002
5. A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box
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