Author:
Slegel T.J.,Averill R.M.,Check M.A.,Giamei B.C.,Krumm B.W.,Krygowski C.A.,Li W.H.,Liptay J.S.,MacDougall J.D.,McPherson T.J.,Navarro J.A.,Schwarz E.M.,Shum K.,Webb C.F.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
171 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03
2. DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
3. A cycle-level recovery method for embedded processor against HT tamper;Heliyon;2023-06
4. Fault Tolerant Architectures;Handbook of Computer Architecture;2023
5. A Novel Fast Recovery Method for HT Tamper in Embedded Processor;Blockchain Technology and Emerging Technologies;2023