Scalable FPGA Hardware Accelerator for SVM Inference-Reference-Cited by-同舟云学术

Scalable FPGA Hardware Accelerator for SVM Inference

Published:2022-06-07 Issue: Volume: Page:
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Container-title:2022 11th Mediterranean Conference on Embedded Computing (MECO)
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Author:

Aftowicz Marcin¹,Lehniger Kai¹,Langendoerfer Peter¹

Affiliation:

1. IHP – Leibniz-Institut für innovative Mikroelektronik,Frankfurt (Oder),Germany

Funder

Federal Ministry of Education and Research

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9797068/9797069/09797110.pdf?arnumber=9797110

Reference15 articles.

1. FPGA Implementations of SVM Classifiers: A Review

2. Hardware Acceleration of SVM-Based Classifier for Melanoma Images

3. SCoPE: Towards a Systolic Array for SVM Object Detection

4. A sum of absolute differences implementation in FPGA hardware

5. Implementation of systolic array based SVM classifier using multiplierless kernel;bhaswati;Proceedings of the 16th international conference on automatic control modelling and simulation (ACMOS '14),0

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