A 510 $\mu$W 0.738-mm$^{2}$ 6.2-pJ/SOP Online Learning Multi-Topology SNN Processor With Unified Computation Engine in 40-nm CMOS-Reference-Cited by-同舟云学术

A 510 $\mu$W 0.738-mm$^{2}$ 6.2-pJ/SOP Online Learning Multi-Topology SNN Processor With Unified Computation Engine in 40-nm CMOS

Published:2023-06 Issue:3 Volume:17 Page:507-520
ISSN:1932-4545
Container-title:IEEE Transactions on Biomedical Circuits and Systems
language:
Short-container-title:IEEE Trans. Biomed. Circuits Syst.

Author:

Fang Chaoming¹^ORCID,Wang Chuanqing²^ORCID,Zhao Shiqi²^ORCID,Tian Fengshi³,Yang Jie²^ORCID,Sawan Mohamad²^ORCID

Affiliation:

1. Zhejiang University, Hangzhou, China

2. Center of Excellence in Biomedical Research on Advanced Integrated-on-chips Neurotechnologies (CenBRAIN Neurotech), School of Engineering, Westlake University, Hangzhou, China

3. Hong Kong University of Science and Technology, Hong Kong SAR, China

Funder

Westlake University

STI2030-Major Projects

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Biomedical Engineering

Link

http://xplorestaging.ieee.org/ielx7/4156126/10179952/10132492.pdf?arnumber=10132492

Reference35 articles.

1. The SpiNNaker Project

2. SNPU: Always-on 63.2μW Face Recognition Spike Domain Convolutional Neural Network Processor with Spike Train Decomposition and Shift-and-Accumulation Unit

3. A New Spiking Convolutional Recurrent Neural Network (SCRNN) With Applications to Event-Based Hand Gesture Recognition

4. A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

5. Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation

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