Survey of Shared Register File design for Unified Shader Array in GPUs-Reference-Cited by-同舟云学术

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Survey of Shared Register File design for Unified Shader Array in GPUs

Published:2022-06 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 9th International Conference on Cyber Security and Cloud Computing (CSCloud)/2022 IEEE 8th International Conference on Edge Computing and Scalable Cloud (EdgeCom)
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Author:

Ze Tian¹,Jun Zhang¹,Xianglong Ren¹,Feihu Fan¹,Yue Chen²

Affiliation:

1. Xi’an Xiang Teng Micro-Electronic Technology Co., Ltd,Xi’an, 710068,China

2. Key Laboratory of Aviation Science and Technology on Integrated Circuit and Micro-System Desigen,Xi’an, 710068,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9842862/9842867/09843024.pdf?arnumber=9843024

Reference40 articles.

1. Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG

2. A locality-aware memory hierarchy for energy-efficient GPU architectures

3. Design and implementation of GPU pixel engine[J];zhenqing;Ship Electronic Engineering,2015

4. An architecture of graphics accelerator and shader[J];jungang;Journal of Computer Aided Design and Graphics,2010

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit;IET Circuits, Devices & Systems;2023-10-31

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