1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus-Reference-Cited by-同舟云学术

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1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

Published:2001-05 Issue:5 Volume:36 Page:752-760
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zerbe J.L.,Chau P.S.,Werner C.W.,Thrush T.P.,Liaw H.J.,Garlepp B.W.,Donnelly K.S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/19874/00918912.pdf?arnumber=918912

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04

3. 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links;IEEE Journal of Solid-State Circuits;2021-02

4. Receiver Fundamentals;Analysis and Design of Transimpedance Amplifiers for Optical Receivers;2017-09-22

5. Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-08

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