A 0.1–3.5-GHz Inductorless Noise-Canceling CMOS LNA With IIP3 Optimization Technique-Reference-Cited by-同舟云学术

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A 0.1–3.5-GHz Inductorless Noise-Canceling CMOS LNA With IIP3 Optimization Technique

Published:2022-06 Issue:6 Volume:70 Page:3234-3243
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Zhou Rong¹,Liu Shubin¹^ORCID,Liu Jiye¹^ORCID,Liang Yuhua¹,Zhu Zhangming¹

Affiliation:

1. Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China

Funder

National Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Innovation Fund of Xidian University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/9788475/09745993.pdf?arnumber=9745993

Reference32 articles.

1. A Wideband CMOS Noise-Canceling Low-Noise Amplifier With High Linearity

2. Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique

3. A CMOS Wideband Highly Linear Low-Noise Amplifier for Digital TV Applications

4. Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

5. A 0.061-mm² 1–11-GHz Noise-Canceling Low-Noise Amplifier Employing Active Feedforward With Simultaneous Current and Noise Reduction

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